Dual power supply memory array having a control circuit that dyanmically selects a lower of two supply voltages for bitline pre-charge operations and an associated method

ABSTRACT

Disclosed is a memory array in which the lower of two supply voltages from two power supplies is dynamically selected for bitline pre-charge operations. In the memory array, a voltage comparator compares the first supply voltage on a first power supply rail to a second supply voltage on a second power supply rail and outputs a voltage difference signal. If the voltage difference signal has a first value indicating that the first supply voltage is equal to or less than the second supply voltage, than a control circuit ensures that the complementary bitlines connected to a memory cell are pre-charged to the first supply voltage. If the voltage difference signal has a second value indicating that the first supply voltage is greater than the second supply voltage, then the control circuit ensures that the complementary bitlines are pre-charged to the second supply voltage. Also disclosed is an associated method.

BACKGROUND

1. Field of the Invention

The embodiments disclosed herein relate to dual power supply memoryarrays and, more particularly, to a dual power supply memory arrayhaving a control circuit that dynamically selects the lower of twosupply voltages for bitline pre-charge operations and an associatedmethod.

2. Description of the Related Art

Those skilled in the art will recognize that size and power scaling arekey factors considered in modern integrated circuit design. One commontechnique for power scaling is to reduce the supply voltage. However,with memory cells, such as static random access memory (SRAM) cells,reducing the supply voltage can increase susceptibility to stabilityfailures (i.e., memory fails). Thus, memory arrays (e.g., SRAM arrays)have been developed that incorporate two power supply rails (i.e., afirst power supply rail and a second power supply rail). The first powersupply rail can be configured to have a first supply voltage and thesecond power supply rail can be configured to have a second supplyvoltage that is greater than the first supply voltage. In this case, thesecond or higher supply voltage (e.g., a cell supply voltage (Vcs)) ofthe second power supply rail can be used for memory cell operations,including wordline activation, and the first or lower supply voltage(e.g., a logic supply voltage (Vdd)) of the first power supply rail canbe used for all other memory array operations, including bitlinepre-charging operations. Using the second or higher supply voltage formemory cell operations avoids stability fails and using the first orlower supply voltage for all other operations allows for reduced powerconsumption when having a high supply voltage is not critical.

Unfortunately, power supply noise may cause the values of the firstand/or second supply voltages to fluctuate such that at times the firstsupply voltage (Vdd) used for bitline pre-charge operations is in factgreater than the second supply voltage (Vcs) used for memory celloperations. If this occurs, stability fails can occur. Currently-usedsolutions for avoiding such stability fails include increasing the powerto the second power supply rail (Vcs) so that the first supply voltage(Vdd) will never go above it and/or adding decoupling capacitors to thememory array so that power supply noise is minimized; however, suchsolutions are costly in terms of power and area consumption. Therefore,there is a need in the art for a dual power supply memory array and amethod of operating the array that avoids stability fails withoutresulting in significant power and/or area penalties.

SUMMARY

In view of the foregoing, disclosed herein are embodiments of a dualpower supply memory array in which the lower of two supply voltages fromtwo power supplies is dynamically selected for bitline pre-chargeoperations in order to avoid stability fails without causing significantpower and/or area penalities. Specifically, the memory array canincorporate a voltage comparator and a control circuit. The voltagecomparator can compare the first supply voltage on a first power supplyrail to a second supply voltage on a second power supply rail and canoutput a voltage difference signal. If the voltage difference signal hasa first value indicating that the first supply voltage is equal to orless than the second supply voltage, the control circuit can ensure thatthe complementary bitlines connected to a memory cell are pre-charged tothe first supply voltage. However, if the voltage difference signal hasa second value indicating that the first supply voltage is greater thanthe second supply voltage, the control circuit can ensure that thecomplementary bitlines are pre-charged to the second supply voltage.Also disclosed herein are associated embodiments of a method forpre-charging complementary bitlines connected to a memory cell of amemory array by dynamically selecting between the lower of two supplyvoltages.

More particularly, disclosed herein are embodiments of a dual powersupply memory array in which the lower of two supply voltages from twopower supplies is dynamically selected for bitline pre-charge operationsin order to avoid stability fails without causing significant powerand/or area penalties.

In each of the embodiments, the dual power supply memory array cancomprise a plurality of individually addressable memory cells (e.g.,static random access memory (SRAM) cells) arranged in rows and columns.Each memory cell in a given column can be connected to a pair ofcomplementary bitlines. Additionally, each memory cell in a given rowcan also be connected to a wordline.

In addition, in each of the embodiments, the dual power supply memoryarray can comprise a first power supply rail, a second power supplyrail, a voltage comparator and a control circuit. The first power supplyrail can provide a first supply voltage and the second power supply railcan provide a second supply voltage. The voltage comparator can comparethe first supply voltage to the second supply voltage and can output avoltage difference signal. This voltage difference signal can have afirst value when the first supply voltage on the first power supply railis equal to or less than the second supply voltage on the second powersupply rail and can have a second value when the first supply voltage isgreater than the second supply voltage. If the voltage difference signalhas the first value, the control circuit can ensure that thecomplementary bitlines connected to a memory cell are pre-charged to thefirst supply voltage. However, if the voltage difference signal has thesecond value, the control circuit can ensure that the complementarybitlines are pre-charged to the second supply voltage.

Specifically, in one embodiment, the control circuit can receive thevoltage difference signal and can perform the following based on thevalue of that voltage difference signal. When the voltage differencesignal has the first value, the control circuit can pre-charge thecomplementary bitlines to the first supply voltage by electricallyconnecting the complementary bitlines to the first power supply rail.However, when the voltage difference signal has the second value, thecontrol circuit can pre-charge the complementary bitlines to the secondsupply voltage by electrically connecting the complementary bitlines tothe second power supply rail.

In another embodiment, the control circuit can pre-charge thecomplementary bitlines to the second supply voltage in multiple stages.That is, as in the previously described embodiment, when the voltagedifference signal has the first value, the control circuit canpre-charge the complementary bitlines to the first supply voltage byelectrically connecting the complementary bitlines to the first powersupply rail. However, when the voltage difference signal has the secondvalue, the control circuit can electrically connect the complementarybitlines to the first power supply rail to initiate pre-charging of thecomplementary bitlines. Then, after a period of time, the controlcircuit can electrically connect the complementary bitlines to thesecond power supply rail so as to finish pre-charging the complementarybitlines to the second supply voltage.

Also disclosed herein are embodiments of an associated method forpre-charging complementary bitlines, which are connected to a memorycell of a memory array, to the lower of two supply voltages from twopower supplies. Specifically, in each of the method embodiments, a firstsupply voltage of a first power supply rail is compared (e.g., by avoltage comparator) to a second supply voltage of a second power supplyrail and a voltage difference signal is output. This voltage differencesignal can have a first value when the first supply voltage is equal toor less than the second supply voltage and can have a second value whenthe first supply voltage is greater than the second supply voltage.

Then, in each of the method embodiments, the voltage to which thecomplementary bitlines are pre-charged will depend on the value of thevoltage difference signal. For example, in one embodiment, when thevoltage difference signal has the first value, the complementarybitlines can be pre-charged to the first supply voltage by electricallyconnecting the complementary bitlines to the first power supply rail.However, when the voltage difference signal has the second value, thecomplementary bitlines can be pre-charged to the second supply voltageby electrically connecting the complementary bitlines to the secondpower supply rail. In another embodiment, pre-charging the complementarybitlines to the second supply voltage can be a two-stage process. Thatis, like the previously described embodiment, when the voltagedifference signal has the first value, the complementary bitlines can bepre-charged to the first supply voltage by electrically connecting thecomplementary bitlines to the first power supply rail. However, when thevoltage difference signal has the second value, the complementarybitlines can be electrically connected to the first power supply rail toinitiate pre-charging. Then, after a period of time, the complementarybitlines can be electrically connected to the second power supply railso as to finish pre-charging the complementary bitlines to the secondsupply voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments herein will be better understood from the followingdetailed description with reference to the drawings, which are notnecessarily drawing to scale and in which:

FIG. 1 is a schematic diagram illustrating an embodiment of a dual-powersupply memory array;

FIG. 2 is a schematic diagram illustrating an exemplary memory cell thatcan be incorporated into the memory array of FIG. 1;

FIG. 3 is a schematic diagram illustrating an exemplary voltagecomparator that can be incorporated into the memory array of FIG. 1;

FIG. 4 is a schematic diagram illustrating an exemplary pre-chargecontrol circuit that can be incorporated into the memory array of FIG.1;

FIG. 5 is a schematic diagram illustrating another exemplary pre-chargecontrol circuit that can be incorporated into the memory array of FIG.1; and

FIG. 6 is a flow diagram illustrating a method embodiment forpre-charging complementary bitlines in the memory array of FIG. 1.

DETAILED DESCRIPTION

As mentioned above, size and power scaling are key factors considered inmodern integrated circuit design. One common technique for power scalingis to reduce the supply voltage. However, with memory cells, such asstatic random access memory (SRAM) cells, reducing the supply voltagecan increase the susceptibility to stability failures (i.e., memoryfails). Thus, memory arrays (e.g., SRAM arrays) have been developed thatincorporate two power supply rails (i.e., a first power supply rail anda second power supply rail). The first power supply rail can beconfigured to have a first supply voltage and the second power supplyrail can be configured to have a second supply voltage that is greaterthan the first supply voltage. In this case, the second or higher supplyvoltage (e.g., a cell supply voltage (Vcs)) of the second power supplyrail can be used for memory cell operations, including wordlineactivation, and the first or lower supply voltage (e.g., a logic supplyvoltage (Vdd)) can be used for all other memory array operations,including bitline pre-charging operations. Using the second or highersupply voltage for memory cell operations avoids stability fails andusing the first or lower supply voltage for all other operations allowsfor reduced power consumption when having a high supply voltage is notcritical.

Unfortunately, power supply noise may cause the values of the firstand/or second supply voltages to fluctuate such that at times the firstsupply voltage (Vdd) used for bitline pre-charge operations is in factgreater than the second supply voltage (Vcs) used for memory celloperations. If this occurs, stability fails can occur. Currently-usedsolutions for avoiding such stability fails include increasing the powerto the second power supply rail (Vcs) so that the first supply voltage(Vdd) will never go above it and/or adding decoupling capacitors to thememory array so that power supply noise is minimized; however, suchsolutions are costly in terms of power and area consumption.

More particularly, referring to FIG. 1, disclosed herein are embodimentsof a dual power supply memory array 100. As with a conventional memoryarray, the memory array 100 can comprise a plurality of memory cells110, which are arranged in columns and rows and peripheral circuitry(e.g., an address decode 140, write drivers 120, sense amplifiers 130,etc.) that facilitates writing data values to and reading data valuesfrom the memory cells 110.

Referring to FIG. 2 in combination with FIG. 1, each memory cell 110can, for example, comprise a static random access memory (SRAM) cell,such as a six transistor (6T) SRAM cell. A 6T SRAM cell typicallycomprises a pair of access transistors (also referred to as pass-gatetransistors) 201 a, 201 b (e.g., N-type field effect transistors) and apair of cross-coupled inverters. Each inverter can comprise a pull-uptransistor 211 a, 211 b (e.g., a P-type field effect transistor)connected in series to a pull-down transistor 212 a, 212 b (e.g., anN-type field effect transistor). The drain of one of the accesstransistors (e.g., access transistor 201 a) is connected to a node 213 abetween the pull-up and pull-down transistors 211 a and 212 a of one ofthe inverters and the drain of the other access transistor (e.g., accesstransistor 201 b) is connected to a node 213 b between the pull-up andpull-down transistors 211 b and 212 b, of the other inverter.Furthermore, the source of one of the access transistors (e.g., accesstransistor 201 a) is connected to one bitline of a complementary pair ofbitlines (e.g., the bitline 111 a, which is also referred to as a truebitline (BLT)) and the source of the other access transistor (e.g.,access transistor 201 b) is connected to the other bitline in thecomplementary pair of bitlines (e.g., the bitline 111 b, also referredto as the complementary bitline (BLC)). The gates of the accesstransistors 201 a, 201 b are connected to a wordline (WL) 113.

Such an SRAM cell 110 operates in three different stages: standby, writeand read. In the standby state, the cell is idle. In the write stage, adata value is written into the cell. Specifically, if a data value of“1” (i.e., a high data value) is to be written to the node 213 a, a “1”is applied to the bitline 111 a and a “0” is applied to the bitline 111b. Then, the wordline 113 is activated to enable the access transistors201 a, 201 b and the data value “1” is stored at node 213 a. Contrarily,if a data value of “0” (i.e., a low data value) is to be written to thenode 213 a, a “0” is applied to the bitline 111 a and a “1” is appliedto the bitline 111 b. Then, the wordline 113 is activated to enable theaccess transistors 201 a, 201 b and the data value “0” is stored at node213 a. In the reading stage, the data value stored in the cell is read.Specifically, the bitlines 111 a, 111 b are both pre-charged high (i.e.,to a “1”) and the wordline 113 is activated to enable the accesstransistors 201 a, 201 b. When a data value of “1” is stored on node 213a, bitline 211 a will remain charged at its pre-charge level of “1” andthe bitline 211 b will be discharged to “0” through the transistors 212b and 201 b. When a data value of “0” is stored on node 213 a, bitline111 a will be discharged to “0” through transistors 212 a and 201 a andthe bitline 111 b will remain charged at its pre-charge level of “1”. Asense amplifier 130 at the end of each column will sense whether bitline111 a or 111 b is higher and, thereby will sense the data value storedin the cell 110.

This description of a 6T SRAM cell and its operation is offered forillustration purposes only and is not intended to be limiting. It shouldbe understood that a 6T SRAM cell with an alternative configuration,another type of SRAM cell (e.g., an eight transistor SRAM cell) oranother type of memory cell could alternatively be incorporated into thememory array 100. Furthermore, the above-mentioned peripheral circuitry(e.g., an address decode 140, write drivers 120, sense amplifiers 130,etc.) that can be used to facilitate writing data values to and readingdata values from the memory cells 110 is well-known in the art and,thus, the details thereof are omitted from this specification in orderto allow the reader to focus on the salient aspects of the embodiments.

Referring again to FIG. 1, the memory array 100 can further comprise twopower supply rails (i.e., a first power supply rail 171 and a secondpower supply rail 172). The first power supply rail 171 can beconfigured to have a first supply voltage (e.g., a logic supply voltage(Vdd)) and the second power supply rail 172 can be configured to have asecond supply voltage (e.g., a cell supply voltage (Vcs)). Generally,the first power supply rail 171 and second power supply rail 172 can beset such that the second supply voltage 172 is sufficiently high tosupply power for memory cell operations, including wordline activation,and such that in the absence of noise the first supply voltage, whichcan be used for other memory array operations, is lower than the secondsupply voltage in order to save power. In a conventional dual powersupply memory array, the power supply rail that is set low (e.g., to Vddas compared to Vcs) to reduce save power is typically used for allbitline pre-charge operations. However, as a result of power supplynoise, the voltages on the power supply rails may actually fluctuatesuch that Vdd is the higher of the two voltages (i.e., such thatVdd>Vcs) and this relatively higher charge on the bitlines can overwhelmthe voltages within the memory cells, thereby resulting in stabilityfails. Consequently, rather than forcing the bitlines to always bepre-charged to the first supply voltage (e.g., Vdd) on the first powersupply rail 171, the memory array 100 is configured so that the lower ofthe two supply voltages (e.g., Vdd or Vcs) from the two power supplyrails 171, 172 is dynamically selected for the bitline pre-chargeoperations in order to avoid stability fails.

To accomplish this, the memory array 100 can further comprise at leastone voltage comparator 160 and a plurality of bitline pre-charge controlcircuits 150. The voltage comparator 160 can compare (i.e., can beadapted to compare, can be configured to compare, etc.) the voltages onthe power supply rails 171, 172. Each pre-charge control circuit 150 canbe associated with a corresponding column of memory cells 110 and canpre-charge (i.e., can be adapted to pre-charge, can be configured topre-charge, etc.) the pair of complementary bitlines 111 a, 111 bconnected to the memory cells 110 in that column.

FIG. 3 is a schematic drawing illustrating an exemplary voltagecomparator 160. This voltage comparator 160 can comprise an amplifier orany other suitable device that has dual inputs (e.g., one electricallyconnected to the first power supply rail 171 and the other electricallyconnected to the second power supply rail 172), that can compare (i.e.,that can be adapted to compare, configured to compare, etc.) the firstsupply voltage on the first power supply rail 171 to the second supplyvoltage on the second power supply rail 172 and that can output (i.e.,that can be adapted to output, configured to output, etc.) a voltagedifference signal 165. This voltage difference signal 165 can have afirst value (e.g., a value of “0”, also referred to as a low value) whenthe first supply voltage on the first power supply rail 171 is equal toor less than the second supply voltage on the second power supply rail172 and can have a second value (e.g., a value of “1”, also referred toas a high value) when the first supply voltage is greater than thesecond supply voltage.

FIGS. 4 and 5 are schematic drawings illustrating exemplary pre-chargecontrol circuits 150 a and 150 b, respectively, which can beincorporated into the dual power memory array 100 of FIG. 1. Each ofthese pre-charge control circuits 150 a, 150 b can receive (i.e., can beadapted to receive, configured to receive, wired to receive, etc.) thevoltage difference signal 165 and, based on the value of that voltagedifference signal, can pre-charge the bitlines 111 a and 111 bassociated with the corresponding column of memory cells to the firstsupply voltage (e.g., Vdd) on the first power supply rail 171 or to thesecond supply voltage (e.g., Vcs) on the second power supply rail 172prior to a read operation of particular cell 110 in that column.Specifically, if the voltage difference signal 165 has a first value(e.g., a value of “0” or a low value, indicating that the first supplyvoltage on the first power supply rail 171 is equal to or less than thesecond supply voltage on the second power supply rail 172), the controlcircuit 150 a, 150 b can ensure (i.e., can be adapted to ensure,configured to ensure, etc.) that the complementary bitlines 111 a, 111b, which are connected to the memory cell 110 being read, arepre-charged to the first supply voltage (e.g., Vdd). However, if thevoltage difference signal 165 has a second value (e.g., a value of “1”or a high value, indicating that the first supply voltage on the firstpower supply rail 171 is greater than the second supply voltage on thesecond power supply rail 172), the control circuit 150 a, 150 b canensure (i.e., can be adapted to ensure, configured to ensure, etc.) thatthe complementary bitlines 111 a, 111 b, which are connected to thememory cell 110 being read, are pre-charged to the second supply voltage(e.g., Vcs).

To accomplish this, the pre-charge control circuit 150 a, 150 b cancomprise at least a first NOR gate 151, an inverter 155, and a secondNOR gate 156.

The first NOR gate 151 can receive (i.e., can be adapted to receive,configured to receive, wired to receive, etc.) a bitline restore signal195 and the voltage difference signal 165. The bitline restore signal195 can be generated and output by, for example, array timing controlcircuitry (not shown), and can indicate either that a bitline pre-chargeoperation should be performed (e.g., when the bitline restore signal 195has a value of “0” or a low value) or that a bitline pre-chargeoperation should not be performed (e.g., when the bitline restore signal195 has a value of “1” or a high value). The first NOR gate 151 canperform the NOR logic and can output a first switch enable signal 181whose value depends on the values of the bitline restore signal 195 andvoltage difference signal 165. For example, if the bitline restoresignal 195 and the voltage difference signal 165 both have values of “0”or low values indicating that a bitline pre-charge operation should beperformed and that the bitlines 111 a, 111 b should be pre-charged tothe first voltage on the first power supply rail 171, respectively, thefirst switch enable signal 181 output from the first NOR gate 151 willhave a value of “1” (i.e., a high value). Any other combination ofbitline restore signal and voltage difference signal values will resultin the first switch enable signal 181 having value of “0” (i.e., a lowvalue).

Depending upon its value, the first switch enable signal 181 can resultin activation of first switches 153 a, 153 b to electrically connect thebitlines 111 a, 111 b to the first power supply rail in order topre-charge those bitlines 111 a, 111 b to the first supply voltage(e.g., Vdd). For example, the first switches 153 a, 153 b can compriseP-type field effect transistors (PFETs) connected in series between thefirst power supply rail 171 and the bitlines 111 a, 111 b, respectively.An additional inverter 152 can be connected in series between the firstNOR gate 151 and the gates of the PFETs 153 a, 153 b. This additionalinverter 152 can invert (i.e., can be adapted to invert, configured toinvert, etc.) the first switch enable signal 182 in order to output aninverted first switch enable signal 182 to control the gates of thePFETs 153 a, 153 b. For example, if the resulting inverted first enablesignal 182 has a value of “0” (i.e., a low value), the PFETs 153 a, 153b will be activated and the bitlines 111 a, 111 b will be electricallyconnected to the first power supply rail 171. However, if the resultinginverted first enable signal 182 has a value of “1” (i.e., a highvalue), no such activation of the PFETs 153 a, 153 b will occur.

Additionally, the inverter 155 can receive and invert (i.e., can beadapted to receive and invert, configured to receive and invert, etc.)the voltage difference signal 165 in order to output an inverted voltagedifference signal 185. The second NOR gate 156 can receive (i.e., can beadapted to receive, configured to receive, wired to receive, etc.) boththe bitline restore signal 195 and the inverted voltage differencesignal 185. The second NOR gate 156 can perform the NOR logic and canoutput a second switch enable signal 186 whose value depends on thevalues of the bitline restore signal 195 and inverted voltage differencesignal 185. For example, if the bitline restore signal 195 and theinverted voltage difference signal 165 both have values of “0” (i.e.,low values) indicating that a bitline pre-charge operation should beperformed and that the bitlines 111 a, 111 b should be pre-charged tothe second voltage on the second power supply rail 172, respectively,the second switch enable signal 186 will have a value of “1” (i.e., ahigh value). Any other combination of bitline restore signal andinverted voltage difference signal values will result in the secondswitch enable signal 186 having value of “0” (i.e., a low value).

Referring particularly to the pre-charge control circuit 150 a of FIG.4, in one embodiment, second switches 158 a, 158 b can be activated,depending upon the value of the second switch enable signal 186, inorder to electrically connect the bitlines 111 a, 111 b to the secondpower supply rail 172 and, thereby pre-charge those bitlines 111 a, 111b to the second supply voltage (e.g., Vcs). For example, the secondswitches 158 a, 158 b can comprise P-type field effect transistors(PFETs) connected in series between the second power supply rail 172 andthe bitlines 111 a, 111 b, respectively. A second additional inverter157 can be connected in series between the second NOR gate 156 and thegates of the PFETs 158 a, 158 b. The second additional inverter 157 caninvert (i.e., can be adapted to invert, configured to invert, etc.) thesecond switch enable signal 186 in order to output an inverted secondswitch enable signal 187 to control the gates of the PFETs 158 a, 158 b.For example, if the resulting inverted second enable signal 187 has avalue of “0” (i.e., a low value), the PFETs 158 a, 158 b will beactivated and the bitlines 111 a, 111 b will be electrically connectedto the second power supply rail 172. However, if the resulting invertedsecond enable signal 187 has a value of “1” (i.e., a high value), nosuch activation of the PFETs 158 a, 158 b will occur.

It should be noted that in some cases the second power supply 172 maynot be robust enough to perform the required pre-charging process fromstart to finish and, thus, the pre-charging process may need to beperformed in multiple stages. Thus, referring particularly to thepre-charge control circuit 150 b of FIG. 5, in another embodiment thepre-charging process can be initiated using the first power supply rail171 and subsequently completed using the second power supply rail 172.

Specifically, as mentioned above, when the second switch enable signal186 has a value of “1” (i.e., a high value) the bitlines 111 a, 111 bshould be pre-charged to the second voltage of the second power supplyrail 172. In the embodiment shown in FIG. 5, when the second switchenable signal 186 has a value of “1”, the control circuit 150 b does notsimply connect the bitlines 111 a, 111 b to the second power rail 172.Instead, the control circuit 150 b can electrically connect (i.e., canbe adapted to electrically connect, configured to electrically connect,etc.) the complementary bitlines 111 a, 111 b to the first power supplyrail 171 to initiate the pre-charging process. Then, after a period oftime (e.g., a single logic gate delay), the control circuit 150 b canelectrically connect (i.e., can be adapted to electrically connect,configured to electrically connect, etc.) the complementary bitlines 111a, 111 b to the second power supply rail 172 so as to finishpre-charging process.

To accomplish this, the control circuit 150 b can further compriseadditional switches 159 a, 159 b. Depending upon its value, the secondswitch enable signal 186 can result in activation of the additionalswitches 159 a, 159 b to electrically connect the bitlines 111 a, 111 bto the first power supply rail in order to initiate pre-charging ofthose bitlines 111 a, 111 b. For example, the additional switches 159 a,159 b can comprise N-type field effect transistors (NFETs) connected inseries between the first power supply rail 171 and the bitlines 111 a,111 b, respectively. The second switch enable signal 186 can control thegates of the NFETs 159 a, 159 b. For example, if the resulting secondenable signal 186 has a value of “1” (i.e., a high value), the NFETs 159a, 159 b will be activated and the bitlines 111 a, 111 b will beelectrically connected to the first power supply rail 171. However, ifthe second enable signal 186 has a value of “0”, no such activation ofthe NFETs 159 a, 159 b will occur.

Furthermore, in this embodiment, transmission of the second enablesignal 186 to the additional switches 159 a, 159 b can be performed inparallel with transmission of that same second enable signal 186 to asecond additional inverter 157. Specifically, as with the previouslydescribed embodiment, a second additional inverter 157 can receive thesecond switch enable signal 186, can invert that second switch enablesignal (e.g., from “1” to “0”) and can output an inverted second switchenable signal 187. Activation of the NFETs 159 a, 159 b by the secondenable signal 186 and receipt by the second additional inverter 157 ofthe second enable signal 186 can occur in the same clock cycle. Theinverted second enable signal 187 of “0” can be output one logic-gatedelay later to activate the gates of the PFETs 158 a, 158 b so as toelectrically connect the bitlines 111 a, 111 b to the second powersupply rail 172. Thus, activation of the additional switches 159 a, 159b allows the pre-charging process to be initiated using the first powersupply rail 171 and, then, after a single logic gate delay, activationof the second switches 158 a, 158 b allows the pre-charging process tobe completed using the second power supply rail 172.

Also disclosed herein are embodiments of an associated method forpre-charging complementary bitlines, which are connected to a memorycell of a memory array, to the lower of two supply voltages from twopower supplies. Specifically, referring to FIG. 6 in combination withFIG. 1, the method embodiments can comprise providing a dual powersupply memory array, such as the dual power supply memory array 100described in detail above and illustrated in FIG. 1 (602). In oneembodiment of the method, the dual power supply memory array 100 canincorporate pre-charge control circuits such as the pre-charge controlcircuit 150 a described in detail above and illustrated in FIG. 4. Inanother embodiment of the method, the dual power supply memory array 100can incorporate pre-charge control circuits such as the pre-chargecontrol circuit 150 b described in detail above and illustrated in FIG.5.

In any case, the method embodiments can comprise, prior to pre-charginga complementary pair of bitlines 111 a, 111 b, comparing a first supplyvoltage (e.g., Vdd) of a first power supply rail 171 to a second supplyvoltage (e.g., Vcs) of a second power supply rail 172 in order to outputa voltage difference signal (604). This process 604 can be performed,for example, by a voltage comparator, such as the voltage comparator 160that outputs a voltage difference signal 165, as described in detailabove and illustrated in FIG. 3. This voltage difference signal 165 canhave a first value (e.g., a value of “0”, also referred to as a lowvalue) when the first supply voltage on the first power supply rail 171is equal to or less than the second supply voltage on the second powersupply rail 172 and can have a second value (e.g., a value of “1”, alsoreferred to as a high value) when the first supply voltage is greaterthan the second supply voltage.

Next, based on the value of that voltage difference signal 165, acomplementary pair of bitlines 111 a, 111 b associated with acorresponding column of memory cells can be pre-charged to either thefirst supply voltage (e.g., Vdd) on the first power supply rail 171(608) or to the second supply voltage (e.g., Vcs) on the second powersupply rail 172 prior to a read operation of particular cell 110 in thatcolumn (610).

Specifically, if the voltage difference signal 165 has a first value(e.g., a value of “0” or a low value, indicating that the first supplyvoltage on the first power supply rail 171 is equal to or less than thesecond supply voltage on the second power supply rail 172), thecomplementary bitlines 111 a, 111 b connected to the memory cell 110being read can be pre-charged (e.g., by the control circuit 150 a, 150b) to the first supply voltage (e.g., Vdd) (608). This can beaccomplished by activating switches 153 a, 153 b that electricallyconnect the bitlines 111 a, 111 b, respectively, to the first powersupply rail 171.

If the voltage difference signal 165 has a second value (e.g., a valueof “1” or a high value, indicating that the first supply voltage on thefirst power supply rail 171 is greater than the second supply voltage onthe second power supply rail 172), the complementary bitlines 111 a, 111b associated with the memory cell 110 being read can be pre-charged(e.g., by the control circuit 150 a, 150 b) to the second supply voltage(e.g., Vcs) (610). In one embodiment, this can be accomplished byactivating switches 158 a, 158 b to be electrically connected to thecomplementary bitlines 111 a, 111 b, respectively, to the second powersupply rail 172. However, as discussed in detail above with regard tothe structure embodiments, in some cases the second power supply 172 maynot be robust enough to perform the required pre-charging process fromstart to finish and, thus, the pre-charging process may need to beperformed in multiple stages. In this case, the pre-charging process canbe initiated using the first power supply rail 171 and subsequentlycompleted using the second power supply rail 172. Specifically, switches159 a, 159 b can initially be activated in order to electrically connectthe complementary bitlines 111 a, 111 b, respectively, to the firstpower supply rail 171, thereby initiating the pre-charging process.Then, after a period of time (e.g., a single logic gate delay), switches158 a, 158 b can be activated in order to electrically connect thecomplementary bitlines 111 a, 111 b to the second power supply rail 172in order to finish pre-charging process.

The method embodiments, as described above, are used in the fabricationof integrated circuit chips. The resulting integrated circuit chips canbe distributed by the fabricator in raw wafer form (that is, as a singlewafer that has multiple unpackaged chips), as a bare die, or in apackaged form. In the latter case the chip is mounted in a single chippackage (such as a plastic carrier, with leads that are affixed to amotherboard or other higher level carrier) or in a multichip package(such as a ceramic carrier that has either or both surfaceinterconnections or buried interconnections). In any case the chip isthen integrated with other chips, discrete circuit elements, and/orother signal processing devices as part of either (a) an intermediateproduct, such as a motherboard, or (b) an end product. The end productcan be any product that includes integrated circuit chips, ranging fromtoys and other low-end applications to advanced computer products havinga display, a keyboard or other input device, and a central processor.

It should be understood that the terminology used herein was chosen forthe purpose of describing particular embodiments only and is notintended to be limiting. For example, the singular forms “a”, “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. Additionally, the terms“comprises”, “comprising,” “includes,” and/or “including,” when used inthis specification, specify the presence of stated features, integers,steps, operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof. It shouldfurther be understood that terms such as “right”, “left”, “vertical”,“horizontal”, “top”, “bottom”, “upper”, “lower”, “under”, “below”,“underlying”, “over”, “overlying”, “parallel”, “perpendicular”, etc.,used herein are understood to be relative locations as they are orientedand illustrated in the drawings (unless otherwise indicated). Terms suchas “touching”, “on”, “in direct contact”, “abutting”, “directly adjacentto”, “immediately adjacent to”, etc., mean that at least one elementphysically contacts another element (without other elements separatingthe described elements). Finally, it should be noted that correspondingstructures, materials, acts, and equivalents of all means or step plusfunction elements in the claims below are intended to include anystructure, material, or act for performing the function in combinationwith other claimed elements as specifically claimed. Theabove-descriptions of the various embodiments were presented forpurposes of illustration, but were not intended to be exhaustive. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of theembodiments.

Therefore, disclosed above embodiments of a dual power supply memoryarray in which the lower of two supply voltages from two power suppliesis dynamically selected for bitline pre-charge operations in order toavoid stability fails without causing significant power and/or areapenalities. Specifically, the memory array can incorporate a voltagecomparator and a control circuit. The voltage comparator can compare thefirst supply voltage on a first power supply rail to a second supplyvoltage on a second power supply rail and can output a voltagedifference signal. If the voltage difference signal has a first valueindicating that the first supply voltage is equal to or less than thesecond supply voltage, the control circuit can ensure that thecomplementary bitlines connected to a memory cell are pre-charged to thefirst supply voltage. However, if the voltage difference signal has asecond value indicating that the first supply voltage is greater thanthe second supply voltage, the control circuit can ensure that thecomplementary bitlines are pre-charged to the second supply voltage.Also disclosed herein are associated embodiments of a method forpre-charging complementary bitlines, which are connected to a memorycell of a memory array, by dynamically selecting between the lower oftwo supply voltages.

What is claimed is:
 1. A dual power supply memory array comprising: amemory cell; a pair of complementary bitlines connected to said memorycell; a first power supply rail having a first supply voltage; a secondpower supply rail having a second supply voltage; a voltage comparatorcomparing said first supply voltage to said second supply voltage andoutputting a voltage difference signal, said voltage difference signalhaving a first value when said first supply voltage is any of equal tosaid second supply voltage and less than said second supply voltage andsaid voltage difference signal having a second value when said firstsupply voltage is greater than said second supply voltage; and a controlcircuit performing the following: receiving said voltage differencesignal; when said voltage difference signal has said first value,pre-charging said complementary bitlines to said first supply voltage byelectrically connecting said complementary bitlines to said first powersupply rail; and when said voltage difference signal has said secondvalue, pre-charging said complementary bitlines to said second supplyvoltage by electrically connecting said complementary bitlines to saidsecond power supply rail.
 2. The dual power supply memory array of claim1, said memory cell comprising a static random access memory (SRAM)cell.
 3. The dual power supply memory array of claim 1, furthercomprising a wordline electrically connected to said memory cell.
 4. Thedual power supply memory array of claim 1, said first power supply railand said second power supply rail each being set so that in the absenceof noise said first supply voltage is lower than said second supplyvoltage.
 5. The dual power supply memory array of claim 4, said firstsupply voltage and said second supply voltage fluctuating, due to noiseduring operation of said memory array, such that at times said firstsupply voltage is higher than said second supply voltage.
 6. The dualpower supply memory array of claim 1, said control circuit comprising: afirst NOR gate receiving a bitline restore signal and said voltagedifference signal and outputting a first switch enable signal; aninverter receiving said voltage difference signal and outputting aninverted voltage difference signal; and a second NOR gate receiving saidbitline restore signal and said inverted voltage difference signal andoutputting a second switch enable signal.
 7. The dual power supplymemory array of claim 6, said control circuit comprising: said firstswitch enable signal activating a first switch to electrically connect abitline to said first power supply rail and pre-charge said bitline tosaid first supply voltage, only when said bitline restore signal andsaid voltage difference signal have “0” values; and said second switchenable signal activating a second switch to electrically connect saidbitline to said second power supply rail and pre-charge said bitline tosaid second supply voltage, only when said bitline restore signal andsaid inverted voltage difference signal have “0” values.
 8. A dual powersupply memory array comprising: a memory cell; a pair of complementarybitlines connected to said memory cell; a first power supply rail havinga first supply voltage; a second power supply rail having a secondsupply voltage; a voltage comparator comparing said first supply voltageto said second supply voltage and outputting a voltage differencesignal, said voltage difference signal having a first value when saidfirst supply voltage is any of equal to said second supply voltage andless than said second supply voltage and said voltage difference signalhaving a second value when said first supply voltage is greater thansaid second supply voltage; and a control circuit performing thefollowing: receiving said voltage difference signal; when said voltagedifference signal has said first value, pre-charging said complementarybitlines to said first supply voltage by electrically connecting saidcomplementary bitlines to said first power supply rail; and when saidvoltage difference signal has said second value, electrically connectingsaid complementary bitlines to said first power supply rail to initiatepre-charging of said complementary bitlines; and after a period of time,electrically connecting said complementary bitlines to said second powersupply rail so as to pre-charge said complementary bitlines to saidsecond supply voltage.
 9. The dual power supply memory array of claim 8,said memory cell comprising a static random access memory (SRAM) cell.10. The dual power supply memory array of claim 8, further comprising awordline electrically connected to said memory cell.
 11. The dual powersupply memory array of claim 8, said first power supply rail and saidsecond power supply rail each being set so that in the absence of noisesaid first supply voltage is lower than said second supply voltage. 12.The dual power supply memory array of claim 11, said first supplyvoltage and said second supply voltage fluctuating, due to noise duringoperation of said memory array, such that at times said first supplyvoltage is higher than said second supply voltage.
 13. The dual powersupply memory array of claim 8, said control circuit comprising: a firstNOR gate receiving a bitline restore signal and said voltage differencesignal and outputting a first transistor enable signal; a inverterreceiving said voltage difference signal and outputting an invertedvoltage difference signal; and a second NOR gate receiving said bitlinerestore signal and said inverted voltage difference signal andoutputting a second transistor enable signal.
 14. The dual power supplymemory array of claim 12, said control circuit comprising: a firstinverter and a first P-type transistor connected in series to said firstinverter; an N-type transistor; and a second inverter and a secondP-type transistor connected in series to said second inverter, wherein,when said bitline restore signal and said voltage difference signal arelow, said first inverter receives said first transistor enable signaland outputs an inverted first transistor enable signal that activatessaid first P-type transistor so as to electrically connect a bitline tosaid first power supply rail and pre-charge said bitline to said firstsupply voltage, and wherein, when said bitline restore signal and saidinverted voltage difference signal are low, said second transistorenable signal activates said N-type transistor so as to electricallyconnect said bitline to said first power supply rail initiatepre-charging of said bitline and said second inverter receives saidsecond enable signal and outputs an inverted second transistor enablesignal that activates said second P-type transistor so as toelectrically connect said bitline to said second power supply rail andcomplete pre-charging of said bitline to said second supply voltage. 15.A method for pre-charging complementary bitlines connected to a memorycell of a memory array, said method comprising: comparing a first supplyvoltage of a first power supply rail to a second supply voltage of asecond power supply rail and outputting a voltage difference signal,said voltage difference signal having a first value when said firstsupply voltage is any of equal to said second supply voltage and lessthan said second supply voltage and said voltage difference signalhaving a second value when said first supply voltage is greater thansaid second supply voltage; when said voltage difference signal has saidfirst value, pre-charging said complementary bitlines to said firstsupply voltage by electrically connecting said complementary bitlines tosaid first power supply rail; and when said voltage difference signalhas said second value, pre-charging said complementary bitlines to saidsecond supply voltage by electrically connecting said complementarybitlines to said second power supply rail.
 16. The method of claim 15,said memory cell comprising a static random access memory (SRAM) cell.17. The method of claim 15, said memory array further comprising awordline electrically connected to said memory cell.
 18. The method ofclaim 15, said first power supply rail and said second power supply raileach being set so that in the absence of noise said first supply voltageis lower than said second supply voltage.
 19. The method of claim 18,said first supply voltage and said second supply voltage fluctuating,due to noise during operation of said memory array, such that at timessaid first supply voltage is higher than said second supply voltage. 20.The method of claim 15, when said bitline restore signal and saidvoltage difference signal are low, activating a first switch with afirst switch enable signal to electrically connect a bitline to saidfirst power supply rail and pre-charge said bitline to said first supplyvoltage, and when said bitline restore signal and said inverted voltagedifference signal are low, activating a second switch with a secondswitch enable signal to electrically connect said bitline to said secondpower supply rail and pre-charge said bitline to said second supplyvoltage.
 21. A method for pre-charging complementary bitlines connectedto a memory cell of a memory array, said method comprising: comparing afirst supply voltage on a first power supply rail to a second supplyvoltage on a second power supply rail and outputting a voltagedifference signal, said voltage difference signal having a first valuewhen said first supply voltage is any of equal to said second supplyvoltage and less than said second supply voltage and said voltagedifference signal having a second value when said first supply voltageis greater than said second supply voltage; when said voltage differencesignal has said first value, pre-charging said complementary bitlines tosaid first supply voltage by electrically connecting said complementarybitlines to said first power supply rail; and when said voltagedifference signal has said second value, electrically connecting saidcomplementary bitlines to said first power supply rail to initiatepre-charging of said complementary bitlines; and after a period of time,electrically connecting said complementary bitlines to said second powersupply rail so as to pre-charge said complementary bitlines to saidsecond supply voltage.
 22. The method of claim 21, said memory cellcomprising a static random access memory (SRAM) cell.
 23. The method ofclaim 21 said memory array further comprising a wordline electricallyconnected to said memory cell.
 24. The method of claim 21, said firstpower supply rail and said second power supply rail each being set sothat in the absence of noise said first supply voltage is lower thansaid second supply voltage and said first supply voltage and said secondsupply voltage fluctuating, due to noise during operation of said memoryarray, such that at times said first supply voltage is higher than saidsecond supply voltage.
 25. The method of claim 21, said control circuitcomprising: when said bitline restore signal and said voltage differencesignal are low, inverting a first switch enable signal into an invertedfirst switch enable signal and activating a first P-type transistor withsaid inverted first enable signal so as to electrically connect abitline to said first power supply rail and pre-charge said bitline tosaid first supply voltage, and when said bitline restore signal and saidinverted voltage difference signal are low, activating an N-typetransistor with a second switch enable signal so as to electricallyconnect said bitline to said first power supply rail and initiatepre-charging, inverting said second transistor enable signal into aninverted second transistor enable signal and activating a second P-typetransistor with said inverted second transistor enable signal so as toelectrically connect said bitline to said second power supply rail andcomplete pre-charging of said bitline to said second supply voltage.